1. Field of the Invention
The present invention relates to a conversion apparatus for a sampling frequency in digital signal processing, and more particularly to a sampling frequency conversion apparatus and a fractional frequency dividing apparatus for sampling frequency conversion by which the ratio between frequencies before and after frequency conversion can be set to a non-integer.
2. Description of the Related Art
A sampling frequency conversion apparatus which samples a signal obtained by sampling an original signal with a different sampling frequency again is conventionally known and disclosed, for example, in Japanese Patent Laid-Open Application No. Heisei 6-252749.
FIG. 4 shows a conventional sampling frequency conversion apparatus of the type mentioned above. Referring to FIG. 4, the sampling frequency conversion apparatus shown can provide a plurality of combinations between the sampling frequency of input data and the sampling frequency of output data. In order to generate a clock signal for sampling, a PLL circuit composed of a phase comparator 41, a voltage-controlled oscillator 42 and a frequency divider 43 is used.
The sampling frequency conversion apparatus adopts such a construction that a signal obtained by sampling an original signal with a clock signal of a predetermined clock frequency is inputted as input data to an oversampling circuit 44 so that it is oversampled with a clock signal of another frequency higher than the sampling frequency.
The clock signal for oversampling the input data is inputted to the phase comparator 41 while an output of the voltage-controlled oscillator 42 is inputted to the phase comparator 41 after it is divided by the frequency divider 43 so that the phases of the clock signal and the divided signal are compared with each other by the comparator 41 to produce an error signal. Then, the voltage-controlled oscillator 42 is controlled with the error signal so that a clock signal corresponding to, but having a higher frequency than, the input clock signal is outputted as the clock signal for oversampling from the voltage-controlled oscillator 42 to the oversampling circuit 44.
The sampling frequency conversion apparatus described above has a restriction in that, since the original clock signal and the output of the voltage-controlled oscillator 42 are used as clock signals for sampling, when performing conversion of the sampling frequency utilizing the two clock signals, the ratio between frequencies before and after the frequency conversion must be an integer.
Therefore, with the sampling frequency conversion apparatus described above, where the frequency of the voltage-controlled oscillator side is determined from a demand from a system, there is a limitation in frequency of an oscillator serving as a source oscillator which oscillates the original or reference clock signal. Therefore, it is difficult to use another oscillator, which is used in the system, commonly as the source oscillator.